Quality control for the production of microelectronic devices, such as integrated circuits formed on a semiconductor substrate wafer, depends upon the accurate alignment of each layer over the previously formed layers of the substrate. For example, each device formed on the semiconductor wafer must be properly aligned with respect to the other devices for the integrated circuit to operate properly. Further, each device region must be properly aligned with the other regions of the device for proper operation. Interconnect layers must be properly oriented with respect to underlying layers to ensure proper electrical connections are established. Thus vertical and horizontal alignment of the wafer layers and regions is of utmost importance to ensure successful operation of the integrated circuit. Misaligned layers will cause device regions to be displaced from their proper location, leading to device failure and thus failure of the integrated circuit.
During formation of the integrated circuit, the top wafer layer frequently undergoes a patterning and etching process to remove specific portions thereof. For example, metal layers are patterned and etched to form interconnects between device regions. Insulator layers are patterned and etched to form regions for deposition or implanting of dopants. As new layers are formed, the patterning and etching process is carried out on the top wafer layer. The patterning operation is performed using a mask having transparent and opaque regions for transferring a pattern from the mask to the top surface of the wafer. Conventionally, the mask pattern is first transferred to a layer of photoresist formed on the wafer surface. Photoresist is a light sensitive material such that light exposure changes the material structure and properties. For example, exposure of a negative-acting photoresist to light changes the photoresist from a soluble to an insoluble state, and the soluble regions can be removed with chemical solvents. When a negative-acting photoresist is applied to the top surface of a wafer and exposed to light through a mask, the exposed regions become insoluble. The soluble regions are then removed by chemical solvents. At this point the pattern has been transferred to the wafer surface for subsequent processing. For example, the exposed wafer surface regions can removed by a chemical etching process to which the photoresist is resistant, or dopant ions can be implanted in the exposed regions. After processing of the exposed regions has been completed, the remaining photoresist is removed. Thus it can be seen that the alignment between the mask and the underlying wafer surface must be precise to ensure accurate location of the removed regions relative to the regions previously formed in the wafer.
Semiconductor devices are formed in the integrated circuit by adding impurity dopants such as boron, phosphorus, and arsenic into a germanium or a silicon containing wafer layer to form the semiconductor regions. As is known, compound materials from columns III/IV and II/VI of the periodic table can also be used. Such a doped region may be a gate conductor or a source/drain region of a MOSFET device, for example. One doping process involves placing the wafer in a heated chamber and subjecting it to vapors of the proper dopant. Dopant atoms in the vapor diffuse into exposed regions of the wafer surface to form thin doped regions in the wafer surface. The exposed regions are defined by a previous masking step similar to the patterning and etching steps described above.
Alternatively, doped regions can be formed in the wafer by implantation of an impurity dopant species. The dopant may be introduced using an ion implantation process in which the wafer surface is exposed to bombardment by high energy dopant ions though a pattern of openings formed in a developed layer of the photoresist material. Conventionally, the pattern in the photoresist layer is formed by a photolithographic masking process as described above. The dopant ions penetrate the wafer surface to form implanted regions below the wafer surface, which remain after the layer of photoresist is removed.
Mask processing is also used for patterning metal interconnect layers. A layer of metal is applied to the wafer surface followed by a layer of photoresist. The photoresist is patterned using a masking process, exposed and then the photoresist and the underlying metal are etched. The remaining photoresist material is then removed, leaving a patterned metal layer of interconnect circuitry.
Multiple patterning steps using photolithographic masks as described above are commonplace in the fabrication of integrated circuits. For example, 15 to 20 masking steps may be required in the fabrication of a random access memory (RAM) integrated circuit (IC). The IC can contain tens of millions of individual devices in an area of about 0.25 square inches. Individual feature sizes are in the range of 1 micron and these features must be aligned to within tolerances of about one-third the feature size. This tolerance must be maintained as each level is exposed and formed in the wafer.
Typically, the masks used in the fabrication of an integrated circuit include an alignment mark or target located near the mask edge. Each wafer layer also includes an alignment mark or target. These targets can be formed of metal in metal layers or a doped region in a device layer. Mask alignment is then accomplished by properly positioning the mask target over a corresponding mark on the wafer. As illustrated in FIG. 1, alignment marks can include a cross 10 in the mask for aligning with four spaced apart squares 12 in the top wafer layer, such that the arms of the cross are located in the region between the squares. Another type of alignment mark includes two differently-sized squares that are aligned by placing the smaller square 14 in the middle of the larger square 16. See FIG. 2.
There are several categories of alignment errors. Simple displacement in the x-y direction is probably the most common. FIG. 3 illustrates misalignment in the x direction. In a rotational error condition, one side of the wafer is aligned, but the patterns become increasingly misaligned across the wafer. See FIG. 4. While certain semiconductor processes may utilize one mask to pattern and etch the entire wafer surface, it is more common for a mask to comprise a plurality of smaller masks for patterning and etching one more individual die on the wafer. If the mask patterns are not located on constant centers or are off-center, run-in and run-out alignment problems are created. As shown in FIG. 5, then only a portion of the mask patterns can be properly aligned to the wafer patterns and the pattern becomes progressively misaligned across the wafer.
FIG. 6 is a profile view of the misalignment between a wafer feature 20 and an underlying feature 22. Ideally, the feature 20 should be centered over the feature 22. Alignment error in FIG. 6 is indicated by an arrow 24.
There are several known devices and techniques for aligning the mask and wafer during the fabrication process. In the contact aligner, the wafer is mounted over a vacuum wafer chuck and located below the mask. The operator aligns the mask alignment marks with the marks on the wafer surface by viewing through a microscope and reorienting the wafer as required to bring the marks into alignment. Typically, the wafer and mask each include two sets of alignment marks on opposing sides. The microscope image presents a split field so that these opposing edges can be viewed simultaneously and the wafer adjusted until both sets of marks indicate alignment. Once aligned, the wafer is driven upward into contact with the mask and the wafer photoresist is exposed through the mask.
Modern alignment processes are built into the steppers/repeaters used in most state-of-the-art fabrication facilities. A reticle carrying the pattern of one or more wafer die is aligned with the wafer, the wafer is exposed, the reticle is stepped to the next site and the process is repeated. The result is better overlay and alignment as each die or a plurality of closely spaced dice are individually aligned. As a result, the stepping procedure allows precise alignment over larger diameter wafers. The stepper incorporates an automatic alignment system in which low energy laser beams are passed through alignment marks on the reticle and reflected from corresponding alignment marks on the wafer surface. The resulting signal is analyzed to determine the center of reflections, from which the relative offset is computed. The offset information is input to a computer controlled wafer chuck that moves the wafer relative to the mask until the offset is reduced below a predetermined threshold.
As semiconductor line widths and feature sizes continue to shrink, the disadvantages of state-of-the-art overlay metrology become more pronounced. Accuracy is limited by the overlay feature scale relative to the active area feature scale. The overlay features must be large enough to be optically resolvable by current techniques, but the overlay feature scale is often much larger than the circuit device features. Thus large non-design rule targets or overlay marks are required. In certain processes, accurate overlay is determined by edge detection algorithms, but the associated variability in defining these edges is a disadvantage of the present overlay metrology techniques. Also, the current techniques do not provide any feature profile information that can be useful in determining overlay accuracy.
Process distortions in the overlay marks also lead to misalignment. Because different regions of the optical lens system can be used to expose different areas of the wafer, the alignment across the wafer can be affected by localized lens distortion, focus and illumination conditions. These disadvantages become more prevalent as wave front engineering methodologies, such as phase shift masks become more common.
In conventional semiconductor processing the stepper/repeater performs the alignment and exposure function as the wafer is processed. However, a separate off-line step is used to characterize the overlay misalignment of the mask-printed feature to the underlying feature, i.e., how well did the stepper/repeater align the mask image on the photoresist relative to the wafer features. This overlay characterization is performed off-line with stand-alone optical microscopes, rather than with fabrication-integrated overlay metrology tools.
As is known, the accuracy of the optical overlay system is limited by the wavelength of the light. Particles or surface features smaller than the wavelength cannot be detected. Scanning electron microscopes are also limited in that the electrons do not penetrate the wafer surface and thus it is not possible to align a surface layer with another layer below the surface. However, a scattered beam is not wavelength limited and certain electromagnetic frequencies used in a scatterometry process can penetrate below the wafer surface. Scatterometry metrology is used to measure various wafer characteristics scanning an incident laser beam over the wafer surface. In one form of scatterometry a multiple wavelength beam (i.e., consisting of several frequencies) is incident on a fixed wafer. In another form, a single frequency incident beam is scattered from rotating a wafer. The reflected light is scattered from the surface onto a screen by the microroughness and surface features. A camera captures the screen image and inputs the image data to a microprocessor, where the image is analyzed to reconstruct the surface that produced the particular screen pattern. The scatterometry technique is used to measure grain sizes, contours and critical dimensions on the wafer surface.
U.S. Pat. No. 5,293,216 describes a sensor device for semiconductor manufacturing which operates on the principle of scatterometry. A coherent beam of laser energy is directed toward a semiconductor wafer surface. Coherent and scattered portions of the beam that are reflected by and transmitted through the wafer are measured and analyzed. This device is used to determine the surface roughness and spectral emissivity values of the wafer which is then correlated to a film thickness value.
Other U.S. patents describe other applications of scatterometer systems for measuring surface features on a semiconductor wafer. U.S. Pat. No. 5,923,423 describes a heterodyne scatterometer for detecting and analyzing wafer surface defects. U.S. Pat. No. 5,703,692 describes an optical scatterometer system that provides illumination of a sample at various angles of incidence without the need for rotating the sample. U.S. Pat. No. 6,154,280 describes a system for measuring surface roughness using two separate beams of electromagnetic radiation. Each of the above-described prior art patents are hereby incorporated by reference herein.